The present invention relates to a semiconductor integrated circuit device, such as technology that can be applied particularly effectively to a memory or the like with logic functions constituted based upon a bipolar CMOS-type RAM (random access memory) of an ECL (emitter coupled logic) interface.
When a high-speed computer system is to be constituted, in general, signals of an ECL level are exchanged between a central processing unit (CPU) and storage devices. Signals of the ECL level have an amplitude which is as small as 0.8 volts that the logic high level (or logic low level) can be changed into the logic low level (or logic high level) within a short period of time.
A bipolar static RAM (or an ECL RAM) has been known as a high-speed semiconductor memory device that can be used for the above-mentioned high-speed computer system. The bipolar RAM has memory cells constituted by bipolar transistors and peripheral circuits, and wherein the input/output interface has signals of the ECL levels.
Japanese Patent Laid-Open No. 250583/1987 (laid-open date: Oct. 31, 1987, inventors: Usami et al., assignee: Hitachi, Ltd.) discloses a bipolar static-type RAM having latch circuits for latching address signals of the ECL level supplied from an external unit and a write control signal WE and a signal forming circuit for forming an internal write pulse based upon the latched write control signal WE0 in order to write the data at a high speed into the memory cell of the bipolar-type static RAM.
In recent years, research has been forwarded vigorously to develop semiconductor memory devices constituted by the combination of bipolar transistors and a CMOS (complementary MOS) circuit. U.S. Pat. No. 4,713,796 teaches a static RAM constituted by bipolar transistors and CMOS circuits. A bipolar CMOS static-type RAM of an ECL I/O signal interface has been disclosed in Ogiue et al., "13 nS 500 mW, 64-Kbit ECL RAM Using Hi-BiCMOS Technology", IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 5, October, 1986, pp. 681-685. Further, a dynamic-type RAM employing bipolar transistors and CMOS circuits have been disclosed in Kitsukawa et al., "An Experimental 1-Mbit BiCMOS DRAM", IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, October, 1987, pp. 657-661. In these static RAM and dynamic RAM, the memory cells are formed by CMOS technology. Therefore, the memory cells consume small amounts of electric power, and are highly densely integrated, and have a large capacity. That is, the peripheral circuits consume small amounts of electric power and operate at a high speed such that the peripheral circuits thereof can be formed by the combination of the bipolar transistors and the CMOS circuits.
As described above, a semiconductor memory of the ECL I/O signal interface is advantageous for operating the computer system at high speeds, and it is desired that the semiconductor memory based on the bipolar-CMOS technology also has the ECL I/O signal interface. In fact, the theory announced by Ogiue et al. deals with a bipolar CMOS static RAM of the ECL I/O signal interface. Here, attention should be given to the fact that in the static RAM based on the bipolar CMOS technology, the internal memory cells are constituted by the CMOS technology and whereby it becomes necessary to convert the input signals of the ECL level into the internal signals of the MOS level, i.e., to convert the input signals of the ECL level into the internal signals of a level having an amplitude nearly equal to the power source voltage of the circuit.
The write cycle time and the read cycle time of the semiconductor memory device used for the computer system are shortened with the increase in the operation speed of the computer system. Therefore, it becomes difficult to realize various timing conditions for the control signals of the ECL level such as write control signals WE0 that are input from the central processing unit or the like to the semiconductor memory devices.